IP Cores

Using IP cores for RFSoC development is a common practice. We do not want to reinvent the wheel all the time. It is already painful to get the RFSoC hardware up and running in a research project.

Some useful open-source IP libraries¹:

• 1G/10G/25G Ethernet for Verilog
• AXI Utilities & AXIS Utilities for Verilog

1. All these libraries have been tested by Wuqiong Zhao. ↩